This invention relates to a frequency synthesizer to be used in mobile radio communications, satellite communications, terrestrial microwave communications, and other such radio equipment. More particularly, this invention relates to a frequency synthesizer which operates intermittently to reduce power consumption, but yet which rapidly phase-locks every time power is restored. This invention further relates to a programmable frequency divider used in a frequency synthesizer and more particularly to a programmable frequency divider in which internal conditions thereof can be preset.
Reduced power consumption is a critical necessity in portable telephone sets and other mobile radio transmitter/receivers. The reduction of power consumption for the frequency synthesizers used in such sets is a particularly important challenge. It is desirable to reduce power consumption by both optimizing the circuit structure (e.g., using low power consumption devices), and also by optimizing the circuit operation. One such possible optimization is by operating the circuit intermittently, known as intermittent operation.
The intermittently controlled frequency synthesizers of the prior art, however, have operated poorly. These devices fluctuate in frequency, whenever the power supply is intermittently switched ON/OFF.
Various circuits have been proposed to suppress such fluctuations. These prior art circuits, while they adequately control frequency fluctuations, have not been effective in intermittently controlling the phase-lock of the system. Such an operation will be described hereinafter.
FIG. 1 is a block diagram which shows a basic structure of a prior art intermittent-operation frequency synthesizer.
As shown in FIG. 1, voltage controlled oscillator (abbreviated as VCO) 1 has a frequency control input CTL and an output Fout, produced at a frequency proportional to the voltage of control input CTL. This output is freqency-divided by variable frequency divider 2. Phase comparator 4 compares the phase of the output signals from frequency divider 2 with the phase of the output signals from a reference signal oscillator 3. A signal proportional to the phase difference is output from phase comparator 4, is smoothed by a loop filter 5, and inputted as the voltage control CTL to VCO 1.
Such a construction uses a phase-locked loop (PLL) to minimize the signal proportional to the phase difference, so as to obtain output signals of a relatively stable frequency from the voltage controlled oscillator.
Such an intermittent operation circuit can be controlled in two ways. A first way is called Intermittent PLL operation. According to Intermittent PLL operation, the voltage controlled oscillator (VCO) 1 is maintained in operation at all times. A power source switch 9 (SW in FIG. 1) is controlled by a control circuit 8 such that it intermittently supplies power from the power source 7 to other circuits. A second method of control is by intermittent Oscillation Operation. In this method, the controlling circuit 8 controls the power source switch 9 so as to intermittently supply power to all of the circuits, including VCO 1. Thus VCO 1 is turned on and off along with all other structures.
The controlling methods for both methods are described with reference to FIG. 2.
When the power from power supply 7 is removed from respective circuits, the output signals from phase comparator 4 are blocked by a switch circuit 6, which is provided between the phase comparator and the loop filter 5 and controlled by control circuit 8. Loop filter 5 includes a charging circuit and latches the controlling voltage CTL. The voltage stored in loop filter 5 is continually supplied to VCO 1. The power supply is then suspended for a predetermined period of time. If the power supply to circuits other than VCO 1 are suspended during this time, this becomes an intermittent PLL operation. If the power supply to all the circuits, including VCO 1, are suspended, this becomes an intermittent oscillation operation.
When the power supply is resumed, the switching circuit 6 is closed, to once again transmit the signals from the phase comparator 4 to the loop filter 5. If there is a difference in phase between the output signals from the variable frequency divider 2 and the reference signal oscillator 3, the controlling voltage CTL to VCO 1 will fluctuate in proportion thereto, when switching circuit 6 is closed.
Therefore, before closing switching circuit 6, it is necessary to adjust the phase of the output signals from the variable frequency divider 2 to coincide with the phase of the output signals from reference signal oscillator 3. This can be achieved by two techniques. One technique requires detection of a coincidence in the phases between the two signals, and closes the switching circuit 6 only when the phase coincidence is detected. The other technique actively causes the phases to coincide with each other by using a phase control circuit, then closes switching circuit 6 once the phases coincide.
It has been found to be difficult to detect a coincidence in phase using the above-discussed first technique, however. Therefore, a predetermined allowable phase difference has been conventionally allowed, to facilitate signal detection. For example, the phases can be considered as coincident within an allowable difference of, for instance, 6 sec., in a 800 MHz frequency synthesizer (with a phase comparator reference frequency in a phase comparator of 25 kHz).
The second technique uses control circuit 8 to produce a reset signal to variable frequency divider 2, synchronized with an edge of the output signal from reference oscillator 3 to start the dividing operation. As the phase difference in this case is equivalent to one cycle of the input signals, it becomes approximately 1.3 nsec in a 800 MHz frequency synthesizer. The method, however, inevitably adds a delay to the phase difference, due to the inherent delays of the control circuit 8. For instance, gate propagation delays (10-100 ns per gate) may cause this inherent delay.
A programmable frequency divider suitable for use in the frequency synthesizer will now be described in more detail.
FIG. 3 is a block diagram which shows the basic structure of a programmable frequency divider. This divider comprises a resettable programmable counter 21, used to divide by a programmable ratio, and a division ratio data generator 22.
FIGS. 4 and 5 are time charts showing the resetting operation of programmable counter 22. If a division ratio n is set in advance, programmable counter 22 begins frequency dividing using the frequency division ratio n at time 404, after the reset signal is removed at time 402. Thus, the operation of this circuit is equivalent to the operation of a standard programmable counter. If, for instance, as shown in FIG. 4, the division ratio n is 4, programmable counter 22 outputs a low level only after counting 0, 1, 2,--when the counted value becomes 3. Programmable counter 22 outputs a high level at all other times except when reset. While programmable counter 22 is being reset, the output level is low.
As can be seen from FIG. 4, there is a delay time which elapses from the release of the reset signal at time 402 until time 404 when the dividing operation is actually started. This delay time is equivalent to approximately one cycle of the input clock.
When the clocks are of an extremely high speed, however, there is a longer delay between the removal of the reset signal and the start of counting, due to propagation delays, instruction times and the like. FIG. 5 shows that this delay time between release of reset at time 502 and counting initiation at time 504, may sometimes extend longer than one input clock cycle before the initiation of the dividing operation. This is an especially difficult problem in gigahertz applications, where the clock cycles are in the order of magnitude of nanoseconds (ns).
As shown in the time chart of FIG. 6, frequency division may be initiated with a higher frequency clock, synchronized with the reference signal. If it is desired to phase-lock the frequency dividing signal with the phase of the reference signal, the above mentioned delay time becomes a phase-error. The phase of a frequency divided output can be synchronized by using a function known as a preset function. This preset function can arbitrarily set internal conditions when the frequency dividing operation starts, to initiate a division operation with a predetermined phase.
FIGS. 7A and 7B show time-chart examples of a preset counter and will be used to compare the reset function with the preset function.
FIG. 7A shows the reset function in use. The frequency divider output stays at a low level while reset, and provides pulses of a 50% duty ratio after the reset is released. FIGS. 7A and 7B show the reset signal being released at a first time 702. FIG. 7A begins counting after an elapse of a delay time 704. The counting begins at a lowest possible number (0) and then counts to (3). divided by 1/8 assumes an opposite state at time 706. This output signal is thus the clock divided by 8. However, the phase of this signal is dependent on the delay time 704, and essentially begins a random time after the reset signal ends. Therefore, if the reset signal is synchronized with a reference signal, the output will be phase-offset from this reference signal. FIG. 7B shows the preset function being used. For instance, when the preset value is 1, the frequency divider output is at a high level corresponding to the value when the preset is ON, and starts counting clocks from the value 1. Since the counting starts from a value 1 instead of the value 0, there is a phase offset built-in to this system. When the reset signal goes low at time 702, the output begins immediately counting. The first count signal is a (2), which is produced at time 708. This first counting signal of (2) is substantially synchronized with the (0) of FIG. 7A. It can therefore be seen that the signal of FIG. 7B is phase offset by two clock cycles. Also, the output remains at "1" during reset.
The technique shown in FIG. 7B can be used to synchronize the frequency divider with a reference when the preset is released to resume the frequency dividing operation. To do this, the internal state is preset in advance, deviated by a number of the input clock cycles equivalent to the delay. When the preset is released, the output from the frequency divider becomes synchronized with the reference signal with a phase difference within one cycle of the input clock cycle.
FIG. 8 is a block diagram which shows the basic structure of a programmable frequency divider using a pulse swallowing type programmable counter. This counter includes division ratio data generator 22, and pulse swallowing type programmable counter 25. This device has programmable counter 23 incorporating two counters respectively denoted A and B, and a pre-scaler 24 which can switch the division ratio between the ratios P and P+1. The programmable counter 23 counts the output pulse form the pre-scaler 24 using counters A and B to simultaneously count this output.
The division ratio is initially set at P+1 at the pre-scaler 24.
It is assumed here that the division ratio of the counter A and of the counter B are a and b respectively, with b&gt;a. The counter A therefore counts a number a of output pulses from the pre-scaler 24, and then outputs a pulse to the pre-scaler 24. This revises the division ratio from P+1 to P, and then suspends counting of counter A.
The counter B is simultaneously counting, and counts a number b of output pulses from the pre-scaler 24 before outputting a pulse. However, the number a of the pulses has been frequency divided by P+1 while the number (b - a) of pulses is frequency divided by P, since counter A revises the division after counting a pulse. The division ratio N is therefore expressed as below: EQU N=a (P+1)+(b-a) P=bP+a
Whenever the counter B outputs a pulse, counters A and B and pre-scaler 24 may be all reset. The division ratio of the pre-scaler 24 is therefore set again at P +1 (if reset). Therefore, this pulse swallowing type of programmable counter is generally used for frequency synthesizers of several tens of MHz or higher. When the frequency of the input clock is high, 1/4 or 1/8 radio frequency fixed counters (RF-fixed counters) are generally provided at the stage prior to a programmable counter as a radio frequency-counter. In such a case, the division ratio inevitably becomes a multiple of 4 or 8, making fine precision frequency control difficult. However, if the frequency is not that high, this pulse swallowing method can divide frequency directly and change the frequencies in the whole system separately from each other.
Even in the case of pulse swallowing type programmable counters as described above, the phase of the output from the frequency divider can be, in principle, phase-locked with the reference signal by adding the aforementioned preset function.
However, it has proved extremely difficult in practice to add such a preset function to either of a variable frequency divider or to the pulse swallowing type programmable counter. Such a preset function is quite easy to add to fixed frequency dividers.
More particularly, in order to add a preset function to a pulse swallowing type programmable counter, the pre-scaler also requires a preset function. The addition of a preset function to a pre-scaler for a frequency as high as 1-3 GHz would, however, increase the operation speed and power consumption and thereby deteriorate performance.
Moreover, the programmable counter is typically already equipped with a preset function in order to construct a programmable frequency divider. Addition of another preset function would pose a difficulty and would require extra structure.
The present invention was conceived to eliminate these defects encountered in the prior art frequency synthesizers, and aims at providing a frequency synthesizer which can be set with a phase-lock for reformation of a phase-locked loop at an high speed and with minimum frequency fluctuation.
According to a first aspect of this invention, a preset function is provided on a variable frequency divider having a simple circuit structure. More particularly, the programmable frequency divider of this invention has a division ratio data generator to generate division ratio data and a programmable counter with a reset function to change the division ratio based on the data. A division ratio data latch circuit temporarily retains division ratio data, and a control circuit controls the trigger signals for the division ratio data latch circuit and the division ratio data from the data source so that the division ratio data can be changed. This division ratio is changed to be different in operation for the first cycle after the release of the reset signal than it is after the operation for the second cycle and thereafter. In other words, by simply changing the division ratio when the dividing operation starts, the equivalent of a preset function is added to a programmable frequency divider circuit.
The programmable frequency divider of this invention is unique and distinguishable from the circuits of the prior art. The division ratio data can be reset by detecting output signals from the programmable counter. The circuit, furthermore, has a division ratio for dividing operation in the first cycle after the reset is released, which is different from the division ratio for the dividing operation at the second cycle and thereafter.
The preset function is used, according to the present invention, to determine the initial phase of the output pulses of a programmable frequency divider, when the reset is initially released. The initial phase can be set in units of a cycle of an input clock. If the frequency of the system is high, the cycle of the input clock is short and the phase of the output pulses can thus be controlled with a finer precision. The propagation delay of the reset release signal due to passing several stages of gate circuitry can be offset by this aforementioned preset function.
The division ratio data for the first cycle operation may be chosen arbitrarily, to realize a function similar to the preset function very easily, using this structure.
If such a programmable frequency divider is used for a frequency synthesizer, the division ratio of the programmable frequency divider can be controlled after the release of the reset signal to offset the phase difference caused by the delays in the control circuit.
According to a second aspect of this invention, a frequency synthesizer produces a signal proportional to a phase difference between the phase of the output signals from the reference oscillator and the phase of the output signal from the variable frequency divider structure. This signal is used for blocking a control signal from being transmitted to a loop filter. The control voltage of the voltage controlled oscillator (VCO) which has been charged in the loop filter is therefore retained.
This signal is produced by a phase difference detection structure which detects the phase difference between the output signal from the reference oscillator and the output signal from the variable frequency divider.
The internal condition of the variable frequency divider can be reset. Upon detecting an edge of the output signals from the reference signal oscillator, the reset is released from the variable frequency divider conducting the dividing operation for the first cycle alone. A frequency dividing operation is conducted using the ratio N for a predetermined period at the second cycle and thereafter. A phase difference is detected by a phase detector between the N ratio output phase from the variable frequency divider and the output phase from the reference oscillator. The division ratio N is then set as n.sub.2 for the variable frequency divider based on the result of the above detection.
A function which blocks the phase difference signal from a phase comparator is also provided, to latch the control voltage of the voltage controlled oscillator at a loop filter. The phase difference detection is repeated until the phase difference between the output signals from the reference oscillator and the output signals from the variable frequency divider becomes smaller than a reference value. A switching circuit is then connected to form a closed loop when the phase difference becomes below a predetermined value or immediately after the final phase difference detection.
The frequency synthesizer of this invention is uniquely characterized in that it uses a phase difference detection operation, and that it can control the phase difference between the output signals from the reference signal oscillator and the output signals from the variable frequency divider to be within a reference value.
The frequency synthesizer of this invention is constructed in a manner that the control voltage of the voltage controlled oscillator is retained in a loop filter. The division ratio n of the variable frequency divider is set to n.sub.1 before closing of the loop in order to reset the internal condition of the variable frequency divider. An edge of the outputs or said reference oscillator is detected to release the reset of the variable frequency divider, to conduct dividing operation for the first cycle alone with the division ratio of n.sub.1. The dividing operation is conducted with the ratio of N for the second cycle and thereafter, and the loop is closed immediately after the last of such operations. The phase difference between the output from the reference signal oscillator and the output from the variable frequency divider after division by the ratio N is detected by a phase detector during the N frequency dividing operation immediately after the reset release. The division ratio n is set to n.sub.2 based on the result of the above detection and the variable frequency divider is reset again for the second phase detection. An operation similar to the first is repeated, until a time when the phase difference of the output from the variable frequency divider becomes smaller than the reference value. A closed loop is formed immediately after the final phase detection is conducted. Since the phase detection is conducted during the intermittent operation, the phase difference can be kept constantly under the reference value.
Therefore, irrespective of fluctuations in temperature and voltage, the synthesizer of this invention can constantly establish phase-lock of the loop, at a high speed and with minimal frequency fluctuation.
This invention therefore effectively allows intermittent operation of such a frequency synthesizer and therefore can achieve a reduction of power consumption in the frequency synthesizer.
This invention further permits fast channel switching by charging the control voltage of the voltage controlled oscillator into the loop filter, while the input from the phase comparator is being blocked from the loop filter. The division ratio N at the variable frequency divider is set corresponding to the frequency.
The frequency synthesizer of this invention can effectively reduce the power consumption of devices such as mobile radio communications, satellite communications, terrestrial microwave communications and other systems which operate with radio frequency. For instance, the invention synthesizer may be used in intermittently receiving in an NTT high capacity land mobile communication system, to extend the time available from the battery per one charge by a factor of 1.5 times. It can reduce power consumption by even a larger margin in a radio communication system of a smaller output power, such as office cordless phone systems. This invention method can switch channels at higher speed by charging the control voltage of the voltage controlled oscillator corresponding to another oscillation frequency at a loop filter, while blocking the input from the phase comparator from the loop filter and setting a division ratio of the variable frequency divider corresponding to the particular frequency. All of this can occur at high speeds.
All the control circuits according to this invention can be constructed with digital ICs, to facilitate large scale integration without the necessity of adjustment.